A flexible data-interlacing architecture for full-search block-matching algorithm
YK Lai, LG Chen, YP Lee - Proceedings IEEE International …, 1997 - ieeexplore.ieee.org
YK Lai, LG Chen, YP Lee
Proceedings IEEE International Conference on Application-Specific …, 1997•ieeexplore.ieee.orgThis paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse
for full-search block-matching algorithm. Based on some cascading strategies, the same
chips can be flexibly cascaded for different block sizes, search ranges, and pixel rates. In
addition, the cascading chips can efficiently reuse data to decrease external memory
accesses and achieve a high throughput rate. Our results demonstrate that the architecture
with 2-D data-reuse is a flexible, low-pin-counts, high-throughput, and cascadable solution …
for full-search block-matching algorithm. Based on some cascading strategies, the same
chips can be flexibly cascaded for different block sizes, search ranges, and pixel rates. In
addition, the cascading chips can efficiently reuse data to decrease external memory
accesses and achieve a high throughput rate. Our results demonstrate that the architecture
with 2-D data-reuse is a flexible, low-pin-counts, high-throughput, and cascadable solution …
This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on some cascading strategies, the same chips can be flexibly cascaded for different block sizes, search ranges, and pixel rates. In addition, the cascading chips can efficiently reuse data to decrease external memory accesses and achieve a high throughput rate. Our results demonstrate that the architecture with 2-D data-reuse is a flexible, low-pin-counts, high-throughput, and cascadable solution for full search block-matching algorithm.
ieeexplore.ieee.org
Showing the best result for this search. See all results