A high performance CAVLC encoder design for MPEG-4 AVC/H. 264 video coding applications
CD Chien, KP Lu, YH Shih… - 2006 IEEE International …, 2006 - ieeexplore.ieee.org
CD Chien, KP Lu, YH Shih, JI Guo
2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006•ieeexplore.ieee.orgThis paper presents a high performance VLSI architecture design for MPEG-4 AVC/H. 264
CAVLC encoding. In the proposed design, we propose a forward-based parallel coding
(FPC) technique to increase the data throughput rate. Moreover, two approaches called
arithmetic table elimination (ATE) and fast look-up table matching (FLM) are exploited to
reduce the hardware cost. With the synthesis constraint of 125 MHz clock, the hardware cost
of the proposed design is 9724 gates based on a 0.18/spl mu/m CMOS technology, which …
CAVLC encoding. In the proposed design, we propose a forward-based parallel coding
(FPC) technique to increase the data throughput rate. Moreover, two approaches called
arithmetic table elimination (ATE) and fast look-up table matching (FLM) are exploited to
reduce the hardware cost. With the synthesis constraint of 125 MHz clock, the hardware cost
of the proposed design is 9724 gates based on a 0.18/spl mu/m CMOS technology, which …
This paper presents a high performance VLSI architecture design for MPEG-4 AVC/H.264 CAVLC encoding. In the proposed design, we propose a forward-based parallel coding (FPC) technique to increase the data throughput rate. Moreover, two approaches called arithmetic table elimination (ATE) and fast look-up table matching (FLM) are exploited to reduce the hardware cost. With the synthesis constraint of 125 MHz clock, the hardware cost of the proposed design is 9724 gates based on a 0.18/spl mu/m CMOS technology, which achieves the real-time processing requiremenwat for H.264 video encoding on HD1080 format video.
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