A parallel architecture for real-time video coding
A computing architecture capable of coding video signals in real time is described. The
codec uses several digital signal processors (DSPs) which can be easily programmed to
implement the recent H. 261 algorithm approved by the CCITT. The DSPs are organized as
a single instruction multiple data (SIMD) computing architecture. Every image in a sequence
is divided in regions of horizontal strips and each region is operated by its own processor.
The principle is used in both the encoder and decoder. These local processors code …
codec uses several digital signal processors (DSPs) which can be easily programmed to
implement the recent H. 261 algorithm approved by the CCITT. The DSPs are organized as
a single instruction multiple data (SIMD) computing architecture. Every image in a sequence
is divided in regions of horizontal strips and each region is operated by its own processor.
The principle is used in both the encoder and decoder. These local processors code …
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