A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap

G Jeon, YB Kim - 2017 International SoC Design Conference …, 2017 - ieeexplore.ieee.org
G Jeon, YB Kim
2017 International SoC Design Conference (ISOCC), 2017ieeexplore.ieee.org
This paper presents a quarter-rate 3-tap DFE design for 4Gbps data rate with switched-
capacitors based 1 st speculative tap. We propose a quarter-rate DFE to supplement a
drawback of switched-capacitors based half-rate DFE. In the half-rate DFE, comparators
have not only low input capacitances but also low transconductance (low sensitivity) in order
to eliminate the first post-cursor. Therefore, the comparators need to have enough pull-down
time to make an accurate decision for a bit. The quarter-rate DFE approach has advantages …
This paper presents a quarter-rate 3-tap DFE design for 4Gbps data rate with switched-capacitors based 1 st speculative tap. We propose a quarter-rate DFE to supplement a drawback of switched-capacitors based half-rate DFE. In the half-rate DFE, comparators have not only low input capacitances but also low transconductance (low sensitivity) in order to eliminate the first post-cursor. Therefore, the comparators need to have enough pull-down time to make an accurate decision for a bit. The quarter-rate DFE approach has advantages of enough pull-down time because of operating at lower frequency of each data path and widely opened eye diagram at the output. In addition, it consumes less power than the half-rate DFE. The DFE is simulated with 180nm technology node and 1.8V power supply. The S21 parameter (channel loss) is 27 dB at 4 Gbps data rate, and the power consumption is 14.52 mW.
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