… is closely related to a Hoare-style programming logic for VHDL and real-time systems in …
of VHDL are described. The programming logic and the associated refinement calculus are …

… This article describes a refinement method for VHDL. It is intended to produce behavioural
code that is “correct by construction”, departing from a nonbehavioural specification. It is a …

… code statements of VHDL gives a specification and a refinement calculus for real-time …
obtained constructively via the refinement calculus. The existence of a refinement path from a pure …

… process calculus, from which behaviourally equivalent VHDL code is finally generated,
possibly after some interactive transformation steps. In the verification path of the project, timing …

… The paper presents a VHDL modelling approach for synthesis of a possible architecture for
… The former is a fuzzy calculus processor. The whole architecture is modeled as two VHDL …

… al. for unit delay VHDL, as presented in [6] in functional style, later recast as relational
semantics with a complete axiomatic semantics and refinement calculus in [1, 2, 3]. In [2], time was …

… VHDL, we define a formal model of the VHDL language in Isabelle/HOL. Our model targets
the functional part of VHDL designs … [20] proposed a refinement calculus for VHDL, effectively …

… A different approach to VHDL/ AMN refinement is … VHDL. Future work aims are to produce
a complete formal ASP and emulator and work on research to extend the refinement calculus …

… The synchronous action systems are part of the formal system design using refinement
calculus derivations. A visual tool for describing action systems (synchronous or asynchronous) is …

… and our understanding of the VHDL subset, that our VHDL synthesizer is using. To support
the translation of a formally defined model to VHDL, it would be useful if VHDL would have a …