An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation

D Yang, W Deng, B Liu, AT Narayanan… - 2017 22nd Asia and …, 2017 - ieeexplore.ieee.org
2017 22nd Asia and South Pacific Design Automation Conference (ASP …, 2017ieeexplore.ieee.org
This paper presents an HDL-synthesized injection-locked phase-locked loop using LC-
based DCO for on-chip clock generation. The superior noise performance of the LC-DCO
enables the proposed synthesizable PLL to achieve top performance among the existing
designs. Fabricated in a 65nm CMOS process, this prototype demonstrates a 0.142 ps
integrated jitter at 3.0 GHz and consumes 4.6 mW while only occupying an area of 0.12 mm
2. It achieves a figure of merit (FoM) of-250.3 dB, which is the best for the synthesized PLL …
This paper presents an HDL-synthesized injection-locked phase-locked loop using LC-based DCO for on-chip clock generation. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm CMOS process, this prototype demonstrates a 0.142ps integrated jitter at 3.0GHz and consumes 4.6mW while only occupying an area of 0.12mm2. It achieves a figure of merit (FoM) of -250.3dB, which is the best for the synthesized PLL up-to-date.
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