Decreasing read cell current ( I _CELL ) has become a major trend in nonvolatile memory (NVM). However, a reduced I _CELL leaves the operation of the sense amplifier (SAs) vulnerable to bitline (BL) level offset and SA input offset. Thus, small- I _CELL NVMs suffer from slow read speed or low read yield. In this study, we propose a new current-sampling-based SA (CSB-SA) to suppress the offset due to device mismatch, while maintaining tolerance for insufficient precharge time. These features enable CSB-SA to achieve a read speed 6.3 ×-8.1× faster than previous SAs, for sensing 100 nA I _CELLs on a 2 K-cell bitline. We fabricated a CMOS-logic-compatible, 90 nm, 512 Kb OTP macro, using the CSB-SA. This OTP macro achieves a random access time of 26 ns for reading sub-200 nA I _CELL . Measurements confirm that this 90 nm CSB-SA is also capable of sub-100 nA sensing.