This paper presents an X-band chirp radar transceiver with bandwidth reduction for range detection. The radar transceiver includes a super-heterodyne receiver including an ADC, a direct-digital synthesizer (DDS) based transmitter and a phase-locked loop (PLL) synthesizer. In a modified Weaver architecture, the down-converted baseband signal is further mixed with another chirp signal through stretch processing. The resulting waveform bandwidth is greatly reduced and thus relaxes the power and bandwidth requirements of the on-chip ADC. Therefore, the proposed radar transceiver achieves power and bandwidth reductions without degrading its range resolution. The radar-on-chip (RoC) MMIC was implemented in a 0.13 µm SiGe technology with die area of 3.5 × 2.5 mm 2 . With a 2.2 V supply for analog/RF circuits and a 1.5 V supply for the digital portion, the chip consumes 326 mW in the receive mode and 333 mW in the transmit mode, respectively.