An efficient VLSI architecture for normal I/O order pipeline FFT design

YN Chang - IEEE Transactions on Circuits and Systems II …, 2008 - ieeexplore.ieee.org
… proposed a novel VLSI architecture of the pipeline FFT processor. By … FFT architecture can
be obtained by using the modified feed-forward data commutators. The resulted architecture

[PDF][PDF] Reconfigurable VLSI architecture for FFT processor

TY Sung, HC Hsin, LT Ko - WSEAS International Conference …, 2009 - researchgate.net
FFT processors and programmable FFT processorFFT algorithm and the CORDIC algorithm
are reviewed briefly. In Section 3, the reusable IP 128-point CORDIC-based split-radix FFT

Pipeline and parallel-pipeline FFT processors for VLSI implementations

Wold, Despain - IEEE Transactions on Computers, 1984 - ieeexplore.ieee.org
… of FFT processors to be developed for all of these algorithms. These versions are well suited
for use in VLSI … efficient use of chip I/O bandwidth between the stages of the FFT algorithms. …

A high performance VLSI FFT architecture

K Babionitakis, K Manolopoulos… - 2006 13th IEEE …, 2006 - ieeexplore.ieee.org
VLSI FFT architecture based on combining three consecutive radix-4 stages to result in a
64-point FFT … engines is capable of operating as a stand-alone 64-point FFT processor and can …

High-throughput VLSI architecture for FFT computation

C Cheng, KK Parhi - … Transactions on Circuits and Systems II …, 2007 - ieeexplore.ieee.org
… 2], we can see that the FFT architecture in [3] computes the … The previous VLSI architectures
for FFT implementation have … FFT architectures in this brief can improve the previous FFT

A new approach to pipeline FFT processor

S He, M Torkelson - … Conference on Parallel Processing, 1996 - ieeexplore.ieee.org
… It has been used as the architecture for the initial VLSI implementation of pipeline FFT
processor [3] and massive wafer scale integrattion [9]. However, it suffers from low, 25%, utilization …

VLSI implementation of programmable FFT architectures for OFDM communication system

SY Lee, CC Chen - Proceedings of the 2006 international conference on …, 2006 - dl.acm.org
… The size of FFT processors with power of 2 can be … Based on the programmable SDF
architecture, an FFT processor … An VLSI architecture of 8192-point FFT processor with only power …

Architectures for multiplierless fast Fourier transform hardware implementation in VLSI

W Perera - … on Acoustics, Speech, and Signal Processing, 1987 - ieeexplore.ieee.org
… presents a novel processor for the implementation of multiplierless FFT's in VLSI. The arithmetic
scheme is specially tailored for the simple binary coefficients used for these FFT's, which …

A hardware efficient VLSI architecture for FFT processor in OFDM systems

J Wu, K Liu, B Shen, H Min - 2005 6th International Conference …, 2005 - ieeexplore.ieee.org
… a hardware efficient FFT implementation architecture using a … addressing, continuous flow
FFT processing can be achieved … INTRODUCTION The implementation of an FFT processor is …

Efficient VLSI architectures for fast computation of the discrete Fourier transform and its inverse

CH Chang, CL Wang, YT Chang - … on Signal Processing, 2000 - ieeexplore.ieee.org
… It is therefore necessary to develop appropriate DFT or FFT processors that can balance the
tradeoff between the chip area and the processing speed. There have been several memory-…