An automatic offset compensation scheme for two-stage operational amplifiers is described. The presented technique can be applied to an existing OA core cell without modifying its design. Offset voltage is reduced by digitally adjusting the resulting offset current at the node between the first and second OA stages. A background calibration is achieved by using a ping-pong structure that improves the temperature stability and an on-demand calibration is also provided. The proposed circuit has been fabricated in a 0.7 /spl mu/m digital CMOS technology. The measured input offset voltage of the test circuits are less than /spl plusmn/200 /spl mu/V.