This paper presents an analog layout placement flow based on Satisfiability Modulo Theories (SMT). For each building sub-block, different layout realizations are generated with different aspect ratio. The flow exploits the sub-block shape functions to explore placements that fulfill the given placement constraints attached to the building sub-blocks, as well as the top-level layout aspect ratio. For placement optimization, different variants are generated for each valid placement consisting of a group of sub-block aspect ratios. Solutions are chosen based on minimum area and verified by post-layout simulations. Using SMT algorithms guarantees generating a solution if one exists while maintaining a very rapid run time. A two stage single ended OTA design using a 65nm process is used to demonstrate the flow with post-layout results.