Design and evaluation of radiation-hardened standard cell flip-flops

…, M Andjelković, A Breitenreiter… - … on Circuits and …, 2021 - ieeexplore.ieee.org
Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective
solution for space applications. In this paper we demonstrate how a standard non-rad-…

Fast error propagation probability estimates by answer set programming and approximate model counting

A Breitenreiter, M Andjelković, O Schrape… - IEEE Access, 2022 - ieeexplore.ieee.org
We present a method employing Answer Set Programming in combination with Approximate
Model Counting for fast and accurate calculation of error propagation probabilities in digital …

Design concept for radiation-hardening of triple modular redundancy TSPC flip-flops

…, M Andjelković, A Breitenreiter… - 2020 23rd Euromicro …, 2020 - ieeexplore.ieee.org
A robust design, which is one of the main requirements for space applications is always a
tradeoff between power and area budget, speed requirement and the overall reliability. The …

Reliability analysis in less than 200 lines of code

A Breitenreiter, O Schrape… - 2021 IEEE 12th Latin …, 2021 - ieeexplore.ieee.org
Answer Set Programming (ASP) is proposed as a compact and versatile approach to circuit
analysis. By the example of upsets in registers we demonstrate how to perform reliability …

Power-and Area-optimized Neural Network IC-Design for Academic Education

F Frankreiter, A Breitenreiter… - 2021 28th IEEE …, 2021 - ieeexplore.ieee.org
A shortage of practically skilled computer science graduates affects academia as well as the
industry. Especially when it comes to hardware design and awareness about the complete …

Radiation-hardness-by-design latch-based triple modular redundancy flip-flops

O Schrape, A Breitenreiter, C Schulze… - 2021 IEEE 12th Latin …, 2021 - ieeexplore.ieee.org
The paper presents an alternative Single-Event Effect (SEE)-tolerant Triple Modular Redundancy
(TMR) circuit topology for space applications. The proposed D-flip-flop circuit scheme …

Machine learning approach for accelerating simulation-based fault injection

L Lu, J Chen, A Breitenreiter, O Schrape… - 2021 IEEE Nordic …, 2021 - ieeexplore.ieee.org
Simulation-based fault injection is an approach, which is usually conducted in the design
phase to evaluate the reliability of circuits. However, this approach is frequently time-consuming…

Laser Fault Injection Attacks against Radiation Tolerant TMR Registers

D Petryk, Z Dyka, I Kabin, A Breitenreiter… - 2022 IEEE 23rd …, 2022 - ieeexplore.ieee.org
Security requirements for the Internet of things (IoT), wireless sensor nodes, and other wireless
devices connected in a network for data exchange are high. Confidentiality, data integrity, …

D-SET mitigation using common clock tree insertion techniques for triple-clock TMR flip-flop

O Schrape, A Breitenreiter… - 2018 21st Euromicro …, 2018 - ieeexplore.ieee.org
The paper presents a strategy for mitigation of SETs on a data path using three-clock input
TMR (Triple Modular Redundancy) flip-flop cells (φTMR approach) as an alternative to the …

SET and SEU Hardened Clock Gating Cell

…, O Schrape, A Breitenreiter… - … 38th Conference on …, 2023 - ieeexplore.ieee.org
Clock gating is a common approach for reduction of dynamic power consumption in digital
designs. It is achieved by insertion of special clock gating cells in the circuit, enabling to …