Deep Neural Networks (DNNs) have demonstrated state-of-the-art performance on a broad
range of tasks involving natural language, speech, image, and video processing, and are …

In this paper, we study the problem of placement-driven technology mapping for table-lookup
based FPGA architectures to optimize circuit performance. Early work on technology …

Configurable processors are becoming increasingly popular for modern embedded systems
(especially for the field-programmable system-on-a-chip). While steady progress has been …

Although the emerging three-dimensional integration technology can significantly reduce
interconnect delay, chip area, and power dissipation in nanometer technologies, its impact on …

Conventionally, microarchitecture designs are mainly guided by the maximum throughput (measured
as IPC) and fail to evaluate the impact of architectural decisions on the physical …

This paper studies a natural formulation of the timing driven maze routing problem. A multi-graph
model appropriate for global routing applications is adopted; the model naturally …

Due to the natural interpretation of a circuit as a graph model, a lot of research has been
done on efficiently applying graph-theoretic algorithms to VLSI layout problems. In this thesis, …

Chip multiprocessors (CMPs) provide a scalable means of exploiting thread-level parallelism
for multitasking or multithreaded applications. However, single-threaded applications will …

We study the problem of performing buffer insertion in the context of a given layout. In a practical
situation, there are restrictions on where buffers may be inserted; for instance, it may be …

As microprocessor technology continues to scale into the nanometer regime, recent studies
show that interconnect delay will be a limiting factor for performance, and multiple cycles will …