Using commercial FPGAs in harsh environments such as space applications, enables high processing power. Temporary faults such as single-event upsets, which can be mitigated by well-known methods, are not as critical as permanent faults, since they may endanger the application in case of a defective FPGA. To overcome the impact of permanent faults, we introduce hardware fault detection, isolation, and recovery. In this paper we focus on the first step, the fault detection, performed by an automated test procedure. We separate the procedure in three subtasks: The source file generation, the build process, and the test process itself. With such a modular concept each subtask can be replaced by customized solutions. Each subtask runs autonomous and may be integrated into the automated test procedure. Moreover, our generic design strategy aims to achieve FPGA type and vendor independence, whereby we address SRAM-based FPGAs. We conduct a case study for a Xilinx Artix-7 to evaluate our implementation. In this first verification step, we only consider look-up tables as essential FPGA primitives. We achieve a fault coverage of approx. 96 % with only four bit files and an overall test process time of less than 20 s. The complete test procedure is based on tool command language scripting. Our frame-based fault injection confirms the successful detection of permanent faults within the covered region. Furthermore, we verify the procedure also for a Virtex-5QV.