The environment and constraints for parallel system inter connection networks have changed dramatically since early research into cut-through routers (switches). In early systems, chip transistors were at a premium. MPP systems were often built using single-chip proces- sor nodes closely packed together, constraining communication bisec- tion area. Unabated increases in VLSI density have led to low-cost high- capacity switch buffering, and complex buffer organizations for maximiz- ing throughput are now possible. In today’s parallel systems, the large size of processor nodes effectively eliminates bisection area constraints. Many other network requirements have also arisen within the last few years. We explore these and other challenges that affect design choices and design decisions for contemporary routers.