The increasing significance of Negative Bias Temperature Instability (NBTI) induced device-reliability degradation presents a compelling reason to perform efficient circuit-level reliability tracking. We propose a novel collaborative monitoring frame-work to track circuit level performance degradation caused specifically by NBTI. We use heterogeneous on-chip sensors to measure environmental and stress parameters and a macro-model to map the device-level degradation information into circuit-level reliability estimates. The macro-model is built using curve-fitted data and provides a practical upper bound of the path-delay-degradation to expect under a given set of dynamic parameters which includes operating conditions, process and stress parameters. Through usage of on-chip sensing resources we minimize the need for extensive circuit-specific analyses and also, the pessimism caused by assuming worst-case operating corners. We validate our approach on ISCAS-85 benchmarks and observe excellent correlation (>0.99) between worst-case SPICE observed and model-predicted path-delay degradation.