The presence of large current peaks on the power and ground lines is a serious concern for
designers of synchronous digital circuits. Current peaks are caused by the simultaneous
switching of highly loaded clock lines and by the signal propagation through the sequential
logic elements. In this work we propose a methodology for reducing the amplitude of the
current peaks. This result is obtained by clock skew optimization. We propose an algorithm
that determines the clock arrival time at each flip-flop in order to minimize the current peaks …

The presence of large current peaks on the power and ground lines is a serious concern for
designers of synchronous digital circuits. Current peaks are caused by the simultaneous
switching of highly loaded clock lines and by the signal propagation through the sequential
logic elements. In this work we propose a methodology for reducing the amplitude of the
current peaks. This result is obtained by clock skew optimization. We propose an algorithm
that, for a given clock cycle time, determines the clock arrival time at each flip-flop in order to …