Design and linearity analysis of a M-2M DAC for very low supply voltage
2015 IEEE International Conference on Electronics, Circuits, and …, 2015•ieeexplore.ieee.org
This work presents the design of a 6 bits M-2M ladder Digital-to-Analog Converter (DAC)
proper for operation under supply voltages of 200 mV or lower. Since the MOS transistors
are operating in the subthreshold region under such low supply, the mismatch analysis was
done using an all-region continuous MOSFET model. The performance of the circuit is
evaluated through simulations and the trade-offs between linearity, supply voltage and
sampling rate are investigated in the paper. It is proposed that a 6 bits M-2M DAC operating …
proper for operation under supply voltages of 200 mV or lower. Since the MOS transistors
are operating in the subthreshold region under such low supply, the mismatch analysis was
done using an all-region continuous MOSFET model. The performance of the circuit is
evaluated through simulations and the trade-offs between linearity, supply voltage and
sampling rate are investigated in the paper. It is proposed that a 6 bits M-2M DAC operating …
This work presents the design of a 6 bits M-2M ladder Digital-to-Analog Converter (DAC) proper for operation under supply voltages of 200 mV or lower. Since the MOS transistors are operating in the subthreshold region under such low supply, the mismatch analysis was done using an all-region continuous MOSFET model. The performance of the circuit is evaluated through simulations and the trade-offs between linearity, supply voltage and sampling rate are investigated in the paper. It is proposed that a 6 bits M-2M DAC operating under 200 mV and with sampling rate of 5.1MS/s is feasible using a commercial 130 nm process and standard transistors.
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