Wired‐logic is especially useful when designing fan‐in restricted logic circuits which are implemented with bipolar and MOS transistors. There is, however, little published on the subject outside of the work done by the present authors. In this paper, a method of reducing the levels of circuits by utilizing Wired‐Logic is presented. The method restricts the number of fanins for a gate utilizing Wired‐Logic and transforms circuits using the transduction method optimization. To attain the proper combination of NOR gates and Wired‐OR gates, an algorithm using Wired‐OR gates for the fan‐in restriction is also presented. By performing experiments on third level NOR circuits, the proposed method is comparable to Generalized Serial Duplication which is an efficient serial duplication. The levels of most circuits are reduced by Wired‐OR gates, thereby demonstrating the efficiency of Wired‐Logic. Although connection length is important to LSI, the cost function simplifies circuit levels. Hence, for the purposes of this paper, analysis is expanded to include the cost function.