Design-for-testability for switched-current circuits
M Renovell, F Azaïs, JC Bodin… - Proceedings. 16th IEEE …, 1998 - ieeexplore.ieee.org
M Renovell, F Azaïs, JC Bodin, Y Bertrand
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No. 98TB100231), 1998•ieeexplore.ieee.orgIn this paper a DFT technique is proposed that provides the full controllability and
observability of each memory cell of a switched-current circuit. The technique is proven to be
applicable to any kind of SI circuits, very easy to automate and without any impact on the
circuit performance. Indeed, the hardware configuration of the circuit is preserved and only
the timing configuration is managed to convert the circuit into a fully testable structure in test
mode.
observability of each memory cell of a switched-current circuit. The technique is proven to be
applicable to any kind of SI circuits, very easy to automate and without any impact on the
circuit performance. Indeed, the hardware configuration of the circuit is preserved and only
the timing configuration is managed to convert the circuit into a fully testable structure in test
mode.
In this paper a DFT technique is proposed that provides the full controllability and observability of each memory cell of a switched-current circuit. The technique is proven to be applicable to any kind of SI circuits, very easy to automate and without any impact on the circuit performance. Indeed, the hardware configuration of the circuit is preserved and only the timing configuration is managed to convert the circuit into a fully testable structure in test mode.
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