We discuss the realization of digital arithmetic using analog arrays in the form of Cellular Neural Networks (CNNs). These networks replace the fast switching nodes of logic gates with slewing nodes using current sources driving into capacitors; this provides both low current spikes and low voltage slewing rates, reducing system noise and cross-talk in low-voltage mixed-signal applications. In this paper we generalize the design methodology using a Symbolic Substitution (SS) technique, and we use a recently developed Double-Base Number System (DBNS) to illustrate our design technique. This choice is predicated on the fact that the DBNS representation is naturally 2-dimensional and excites more degrees of freedom in the design space. Spatial configurations of the recognition/replacement patterns used in SS are defined based on the properties of the DBNS arithmetic operation. The SS recognition phases are implemented by dynamic evaluation of simple conditions defined based on an analysis of the cell dynamic routes. The replacement phases are automatically executed through switching current which force the transition of cell state voltage between logic levels. In effect, we build self-timed logic arrays with all nodes in the system under controlled slew. Simulation results from schematic level designs are provided to demonstrate the effectiveness of the technique.