The effectiveness of affinity-based scheduling in multiprocessor network protocol processing (extended version)
… to evaluate affinity -based scheduling of parallel networking. We start with a multiprocessor
… multiprocessor experiments with our parallel z-kernel implementation, designed to measure …
… multiprocessor experiments with our parallel z-kernel implementation, designed to measure …
A paradigm for processing network protocols in parallel
R Duncan, P Jungck, K Ross - … on Algorithms and Architectures for Parallel …, 2010 - Springer
… The model’s key characteristics for protocol processing are as follows: … The next section
reviews other languages for parallel network processing in general and protocol processing in …
reviews other languages for parallel network processing in general and protocol processing in …
The parallel protocol engine
M Kaiserwerth - IEEE/ACM Transactions on Networking, 1993 - ieeexplore.ieee.org
… components also lend themselves to execution in parallel to the actual protocol processing.
… processing times yield a good estimate of the expected performance of our system. In fact, in …
… processing times yield a good estimate of the expected performance of our system. In fact, in …
Evaluating the performance of network protocol processing on multi-core systems
M Faulkner, A Brampton, S Pink - … International Conference on …, 2009 - ieeexplore.ieee.org
… that exist for network protocol processing within a multicore … design faster and more efficient
networked systems, and how … the application and network protocol processing to take place …
networked systems, and how … the application and network protocol processing to take place …
The performance impact of scheduling for cache affinity in parallel network processing
… to be effective the time between rescheduling of the affinity-managed resource must be small
in … are kept busy executing non-protocol processing when not executing protocol code, that …
in … are kept busy executing non-protocol processing when not executing protocol code, that …
Cluster communication protocols for parallel-programming systems
K Verstoep, RAF Bhoedjang, T Rühl, HE Bal… - … on Computer Systems …, 2004 - dl.acm.org
… For many parallel applications, efficient use of a fast … Finding the right trade-off between
protocol processing at the host … , parallel-programming systems, and parallel applications, we …
protocol processing at the host … , parallel-programming systems, and parallel applications, we …
Dynamic workload profiling and task allocation in packet processing systems
Q Wu, T Wolf - … Conference on High Performance Switching and …, 2008 - ieeexplore.ieee.org
… performed on highly parallel, embedded multicore systems. So-… We show the effectiveness
of this approach in an evaluation … an "application" as a protocol processing step or a network …
of this approach in an evaluation … an "application" as a protocol processing step or a network …
On Cache Contention of Parallel Protocol Processing in SMT
Z Zhang, L Guo - 2006 International Conference on …, 2006 - ieeexplore.ieee.org
… , threads can conflict on shared resources. There are many resources shared by threads in
SMT … Since in protocol processing cache miss penalty is the most significant bottleneck of …
SMT … Since in protocol processing cache miss penalty is the most significant bottleneck of …
Parallel architecture support for high-speed protocol processing
TS Chan, I Gorton - Microprocessors and Microsystems, 1997 - Elsevier
… for the overall efficient implementation of a high-speed protocol processing system, studies
… the construction of a highly parallel and scalable protocol processing system. Therefore, if …
… the construction of a highly parallel and scalable protocol processing system. Therefore, if …
[PDF][PDF] Parallelizing Protocol Processing on SMT Processor Efficiently: A FSM Decomposition Approach
P Efficiently - scholar.archive.org
… based parallel processing approach to use sharing cache of SMT processors effectively. …
There are many resources shared by threads in SMT architecture, L1 instruction and data cache…
There are many resources shared by threads in SMT architecture, L1 instruction and data cache…