Efficient AFT implementation in FPGAs to detect potential electromigration failures
SD Rayaprolu, S Vemuru… - 2012 IEEE International …, 2012 - ieeexplore.ieee.org
SD Rayaprolu, S Vemuru, M Niamat
2012 IEEE International Conference on Electro/Information Technology, 2012•ieeexplore.ieee.orgAn efficient and modular architecture is used to implement Arithmetic Fourier Transform
algorithm as a Built-in-Self Test structure to identify electromigration faults in FPGAs. Xilinx
Virtex 5 FPGA, implemented in 65 nm fabrication process, is used to implement BIST and
simulate the electromigration failure mechanisms. Fault signatures are developed for
different interconnect FPGA resources and simulation results are presented.
algorithm as a Built-in-Self Test structure to identify electromigration faults in FPGAs. Xilinx
Virtex 5 FPGA, implemented in 65 nm fabrication process, is used to implement BIST and
simulate the electromigration failure mechanisms. Fault signatures are developed for
different interconnect FPGA resources and simulation results are presented.
An efficient and modular architecture is used to implement Arithmetic Fourier Transform algorithm as a Built-in-Self Test structure to identify electromigration faults in FPGAs. Xilinx Virtex 5 FPGA, implemented in 65 nm fabrication process, is used to implement BIST and simulate the electromigration failure mechanisms. Fault signatures are developed for different interconnect FPGA resources and simulation results are presented.
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