Efficient FPGA design of exception-free generic elliptic curve cryptosystems
K Tanaka, A Miyaji, Y Jin - … on Applied Cryptography and Network Security, 2021 - Springer
K Tanaka, A Miyaji, Y Jin
International Conference on Applied Cryptography and Network Security, 2021•SpringerElliptic curve cryptography (ECC) is one of promising cryptosystems in embedded systems
as it provides high security levels with short keys. Scalar multiplication is a dominating and
time-consuming process that ensures security in ECC. We implement hardware modules for
generic ECC over 256-bit prime fields on field-programmable gate array (FPGA). The key
points in our design are (1) secure and exception-free for any scalar with less memory
usage,(2) long-bit modular arithmetic modules utilizing today's advanced and high …
as it provides high security levels with short keys. Scalar multiplication is a dominating and
time-consuming process that ensures security in ECC. We implement hardware modules for
generic ECC over 256-bit prime fields on field-programmable gate array (FPGA). The key
points in our design are (1) secure and exception-free for any scalar with less memory
usage,(2) long-bit modular arithmetic modules utilizing today's advanced and high …
Abstract
Elliptic curve cryptography (ECC) is one of promising cryptosystems in embedded systems as it provides high security levels with short keys. Scalar multiplication is a dominating and time-consuming process that ensures security in ECC. We implement hardware modules for generic ECC over 256-bit prime fields on field-programmable gate array (FPGA). The key points in our design are (1) secure and exception-free for any scalar with less memory usage, (2) long-bit modular arithmetic modules utilizing today’s advanced and high-performance programmable logic and considering balance between the modules in terms of propagation delay, (3) parallelism extraction inside each elliptic curve point computation as well as between the point computations, and (4) efficient hardware–software co-processing facilitated by application interfaces between a processing core and hardware modules. The evaluation results demonstrate that our design achieves the best performance to existing FPGA designs without using a table for generic ECC.
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