Fpga-based smith-waterman algorithm: Analysis and novel design
Y Yamaguchi, HK Tsoi, W Luk - … , ARC 2011, Belfast, UK, March 23-25 …, 2011 - Springer
Y Yamaguchi, HK Tsoi, W Luk
Reconfigurable Computing: Architectures, Tools and Applications: 7th …, 2011•SpringerThis paper analyses two methods of organizing parallelism for the Smith-Waterman
algorithm, and show how they perform relative to peak performance when the amount of
parallelism varies. A novel systolic design is introduced, with a processing element
optimized for computing the affine gap cost function. Our FPGA design is significantly more
energy-efficient than GPU designs. For example, our design for the XC5VLX330T FPGA
achieves around 16 GCUPS/W, while CPUs and GPUs have a power efficiency of lower …
algorithm, and show how they perform relative to peak performance when the amount of
parallelism varies. A novel systolic design is introduced, with a processing element
optimized for computing the affine gap cost function. Our FPGA design is significantly more
energy-efficient than GPU designs. For example, our design for the XC5VLX330T FPGA
achieves around 16 GCUPS/W, while CPUs and GPUs have a power efficiency of lower …
Abstract
This paper analyses two methods of organizing parallelism for the Smith-Waterman algorithm, and show how they perform relative to peak performance when the amount of parallelism varies. A novel systolic design is introduced, with a processing element optimized for computing the affine gap cost function. Our FPGA design is significantly more energy-efficient than GPU designs. For example, our design for the XC5VLX330T FPGA achieves around 16 GCUPS/W, while CPUs and GPUs have a power efficiency of lower than 0.5 GCUPS/W.
Springer
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