Fast FPGA implementations of Diffie-Hellman on the Kummer surface of a genus-2 curve
P Koppermann, F De Santis, J Heyszl… - Cryptology ePrint …, 2017 - eprint.iacr.org
P Koppermann, F De Santis, J Heyszl, G Sigl
Cryptology ePrint Archive, 2017•eprint.iacr.orgWe present the first hardware implementations of Diffie-Hellman key exchange based on the
Kummer surface of Gaudry and Schost's genus-2 curve targeting a 128-bit security level. We
describe a single-core architecture for low-latency applications and a multi-core architecture
for high-throughput applications. Synthesized on a Xilinx Zynq-7020 FPGA, our architectures
perform a key exchange with lower latency and higher throughput than any other reported
implementation using prime-field elliptic curves at the same security level. Our single-core …
Kummer surface of Gaudry and Schost's genus-2 curve targeting a 128-bit security level. We
describe a single-core architecture for low-latency applications and a multi-core architecture
for high-throughput applications. Synthesized on a Xilinx Zynq-7020 FPGA, our architectures
perform a key exchange with lower latency and higher throughput than any other reported
implementation using prime-field elliptic curves at the same security level. Our single-core …
Abstract
We present the first hardware implementations of Diffie-Hellman key exchange based on the Kummer surface of Gaudry and Schost’s genus-2 curve targeting a 128-bit security level. We describe a single-core architecture for low-latency applications and a multi-core architecture for high-throughput applications. Synthesized on a Xilinx Zynq-7020 FPGA, our architectures perform a key exchange with lower latency and higher throughput than any other reported implementation using prime-field elliptic curves at the same security level. Our single-core architecture performs a scalar multiplication with a latency of 82 microseconds while our multi-core architecture achieves a throughput of 91,226 scalar multiplications per second. When compared to similar implementations of Microsoft’s FourQ on the same FPGA, this translates to an improvement of 48% in latency and 40% in throughput for the single-core and multi-core architecture, respectively. Both our designs exhibit constant-time execution to thwart timing attacks, use the Montgomery ladder for improved resistance against SPA, and support a countermeasure against fault attacks.
eprint.iacr.org
Showing the best result for this search. See all results