This paper describes the methods and simulation techniques used to verify the
microarchitecture design and functional performance of the IBM POWER4 processor and the
POWER4-based Regatta system. The approach was hierarchical, based on but
considerably expanding the practice used for verification of the CMOS-based IBM S/390
Parallel Enterprise Server™ G4. For POWER4, verification began at the abstract, high-level
design phase and continued throughout the designer and unit levels, the multi-unit level …

This paper describes the methods and simulation techniques used to verify the functional
correctness and performance attributes of the IBM POWER5™ microprocessor and the
eServer™ p5 systems based on it. The approaches used were based on migrating the best
practices that had been used to verify the POWER4™ chip. The POWER5 chip design posed
new challenges to the simulation team with the addition of simultaneous multithreading
(SMT) and dynamic power management (DPM). In addition, there was further integration of …