Implementation of low-complexity FIR filters using serial arithmetic
K Johansson, O Gustafsson… - 2005 IEEE International …, 2005 - ieeexplore.ieee.org
K Johansson, O Gustafsson, L Wanhammar
2005 IEEE International Symposium on Circuits and Systems, 2005•ieeexplore.ieee.orgThe effects of digit-size on FIR filters implemented using multiplier block techniques are
studied. Two different multiplier block algorithms are considered, one that minimizes the
number of adders without considering the number of shifts and one that minimizes the
number of shifts while keeping the number of adders low. Results on area, sample rate, and
power consumption are presented, focusing on the arithmetic parts of the FIR filter.
studied. Two different multiplier block algorithms are considered, one that minimizes the
number of adders without considering the number of shifts and one that minimizes the
number of shifts while keeping the number of adders low. Results on area, sample rate, and
power consumption are presented, focusing on the arithmetic parts of the FIR filter.
The effects of digit-size on FIR filters implemented using multiplier block techniques are studied. Two different multiplier block algorithms are considered, one that minimizes the number of adders without considering the number of shifts and one that minimizes the number of shifts while keeping the number of adders low. Results on area, sample rate, and power consumption are presented, focusing on the arithmetic parts of the FIR filter.
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