High level memory management is an important step during the automatic synthesis of application specific micro coded processors aimed at multi-dimensional signal processing in real-time. For given throughput and I/O flow requirements, the objective is to derive the optimal background memory organization where the cost due to storage size and address requirements are minimized. In this paper, a contribution will be proposed to this complex problem. A strategy will be presented to detect the possibility forin-place storage and to deduce thememory requirements for the implementation of numerical matrix type of algorithms on a single ASIC chip.