In this brief, we introduce a priority encoder that uses a novel priority lookahead (PL) scheme
to reduce delays associated with priority propagation. Two priority encoder approaches are …

This paper discusses the many challenges in the design of future nano architectures that
result from the use of nanoelectronic devices. The relations among these challenges are …

In this paper, a novel hybrid wave pipelined bit-pattern associative router (BPAR) is presented.
A router is an important component in communication network systems. The BPAR allows …

This paper will briefly review nanoelectronic challenges while focusing on reliability. We
shall present and analyze a series of CMOS-based examples for addition starting from the …

In this paper we introduce a VLSI priority encoder that uses a novel priority lookahead scheme
to reduce the delay for the worst case operation of the circuit, while maintaining a very low …

In this paper different logic circuit families operating in the subthreshold region are analyzed.
Their performance in terms of power and speed are of particular interest. The study …

This paper explores low power reliable micro-architectures for addition. Power, speed, and
reliability (both defect- and fault-tolerance) are important metrics of system design, spanning …

A VLSI implementation of a programmable pipelined router scheme for parallel machine
interconnection networks is presented in this paper. The implementation is based on a dynamic …

In this paper we are going to explore low-level implementation issues for fault-tolerant adders
based on multiplexing using majority gates (MAJ). We shall analyze the particular case of …

The content addressable memory (CAM) is a memory in which data can be accessed on the
basis of contents rather than by specifying physical address. In the paper, five novel …