User profiles for Javid Jaffari
![]() | Javid JaffariEngineering Manager - Silicon Architect, Meta Platforms Inc Verified email at meta.com Cited by 1091 |
Statistical thermal profile considering process variations: Analysis and applications
The nonuniform substrate thermal profile and process variations are two major concerns in
the present-day ultra-deep submicrometer designs. To correctly predict performance/ leakage/…
the present-day ultra-deep submicrometer designs. To correctly predict performance/ leakage/…
On efficient LHS-based yield analysis of analog circuits
The Latin hypercube sampling (LHS) has been used as a variance-reduction estimation tool
for an efficient sampling-based variability analysis of analog circuits. For a certain …
for an efficient sampling-based variability analysis of analog circuits. For a certain …
Simultaneous reduction of dynamic and static power in scan structures
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic
power has been the dominant part of power dissipation in CMOS circuits, however, in future …
power has been the dominant part of power dissipation in CMOS circuits, however, in future …
On efficient Monte Carlo-based statistical static timing analysis of digital circuits
The Monte-Carlo (MC) technique is a well-known solution for statistical analysis. In contrast
to probabilistic (non-Monte Carlo) statistical static timing analysis (SSTA) techniques, which …
to probabilistic (non-Monte Carlo) statistical static timing analysis (SSTA) techniques, which …
Adaptive sampling for efficient failure probability analysis of SRAM cells
In this paper, an adaptive sampling method is proposed for the statistical SRAM cell analysis.
The method is composed of two components. One part is the adaptive sampler that …
The method is composed of two components. One part is the adaptive sampler that …
Variability-aware design of subthreshold devices
R Jaramillo-Ramirez, J Jaffari… - 2008 IEEE International …, 2008 - ieeexplore.ieee.org
Recently, devices optimized for subthreshold operation have been introduced as potential
construction blocks for digital subthreshold logic circuits. However, for these devices, a strong …
construction blocks for digital subthreshold logic circuits. However, for these devices, a strong …
Variability-aware bulk-MOS device design
As CMOS technology is scaled down toward the nanoscale regime, drastically growing
leakage currents and variations in device characteristics are becoming two important design …
leakage currents and variations in device characteristics are becoming two important design …
Statistical yield analysis and design for nanometer VLSI
J Jaffari - 2010 - uwspace.uwaterloo.ca
Process variability is the pivotal factor impacting the design of high yield integrated circuits
and systems in deep sub-micron CMOS technologies. The electrical and physical properties …
and systems in deep sub-micron CMOS technologies. The electrical and physical properties …
Thermal-aware placement for FPGAs using electrostatic charge model
A thermal-aware placement is proposed for FPGAs to reduce the peak temperature and
maximum on-chip gradient temperature. A new thermal cost is defined for the simulation …
maximum on-chip gradient temperature. A new thermal cost is defined for the simulation …
Switching activity reduction in low power Booth multiplier
A new low power multiplication algorithm for reducing the switching activity through
operand decomposition for Radix-8 Booth multiplier is proposed. The proposed algorithm …
operand decomposition for Radix-8 Booth multiplier is proposed. The proposed algorithm …