DB2 with BLU acceleration: So much more than just a column store
…, D Kalmuk, V KulandaiSamy, J Leenstra… - Proceedings of the …, 2013 - dl.acm.org
DB2 with BLU Acceleration deeply integrates innovative new techniques for defining and
processing column-organized tables that speed read-mostly Business Intelligence queries by …
processing column-organized tables that speed read-mostly Business Intelligence queries by …
IBM POWER8 processor core microarchitecture
…, RJ Eickemeyer, HQ Le, J Leenstra… - IBM Journal of …, 2015 - ieeexplore.ieee.org
The POWER8™ processor is the latest RISC (Reduced Instruction Set Computer)
microprocessor from IBM. It is fabricated using the company's 22-nm Silicon on Insulator (SOI) …
microprocessor from IBM. It is fabricated using the company's 22-nm Silicon on Insulator (SOI) …
IBM POWER7 multicore server processor
…, BJ Ronchetti, J Stuecheli, J Leenstra… - IBM Journal of …, 2011 - ieeexplore.ieee.org
The IBM POWER® processor is the dominant reduced instruction set computing microprocessor
in the world today, with a rich history of implementation and innovation over the last 20 …
in the world today, with a rich history of implementation and innovation over the last 20 …
Ibm power6 accelerators: Vmx and dfu
…, HW Tast, N Mading, J Leenstra… - IBM Journal of …, 2007 - ieeexplore.ieee.org
The IBM POWER6™ microprocessor core includes two accelerators for increasing
performance of specific workloads. The vector multimedia extension (VMX) provides a vector …
performance of specific workloads. The vector multimedia extension (VMX) provides a vector …
A streaming processing unit for a CELL processor
…, R Kim, T Le, P Liu, J Leenstra… - ISSCC. 2005 IEEE …, 2005 - ieeexplore.ieee.org
The design of a 4-way SIMD streaming data processor emphasizes achievable performance
in area and power. Software controls data movement and instruction flow, and improves …
in area and power. Software controls data movement and instruction flow, and improves …
The microarchitecture of the synergistic processor for a cell processor
…, R Kim, T Le, P Liu, J Leenstra… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
This paper describes an 11 FO4 streaming data processor in the IBM 90-nm SOI-low-k process.
The dual-issue, four-way SIMD processor emphasizes achievable performance per area …
The dual-issue, four-way SIMD processor emphasizes achievable performance per area …
POWER7™, a highly parallel, scalable multi-core high end server processor
…, J Friedrich, S Islam, J Kahle, J Leenstra… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
This paper gives an overview of the latest member of the POWER™ processor family,
POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated …
POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated …
BIST power reduction using scan-chain disable in the Cell processor
…, N Maeding, J Leenstra - … IEEE International Test …, 2006 - ieeexplore.ieee.org
Built-in self test is a major part of the manufacturing test procedure for the cell processor.
However, pseudo random patterns cause a high switching activity which is not effectively …
However, pseudo random patterns cause a high switching activity which is not effectively …
Custom circuit design as a driver of microprocessor performance
…, SH Dhong, HP Hofstee, J Leenstra… - IBM Journal of …, 2000 - ieeexplore.ieee.org
This paper presents a survey of some of the most aggressive custom designs for CMOS
processor products and prototypes in IBM. We argue that microprocessor performance growth, …
processor products and prototypes in IBM. We argue that microprocessor performance growth, …
A 1.8-GHz instruction window buffer for an out-of-order microprocessor core
J Leenstra, J Pille, A Muller, WM Sauer… - IEEE Journal of Solid …, 2001 - ieeexplore.ieee.org
To address the challenges in microprocessor designs beyond a gigahertz, an instruction
window buffer (IWB) was designed. The IWB implements the processor parts for renaming, …
window buffer (IWB) was designed. The IWB implements the processor parts for renaming, …