Latch modeling for statistical timing analysis
Latch based circuits are widely adopted in high performance circuits. But there is a lack of
accurate latch models for doing timing analysis. In this paper, we propose a new latch delay
model in the context of SSTA based on a new perspective of latch timing. The proposed
latch model also takes into account the external timing variations such as data slew. The
new latch model is integrated into SSTA by considering the timing analysis of both the
combinational logic network and the clock distribution network simultaneously. The …
accurate latch models for doing timing analysis. In this paper, we propose a new latch delay
model in the context of SSTA based on a new perspective of latch timing. The proposed
latch model also takes into account the external timing variations such as data slew. The
new latch model is integrated into SSTA by considering the timing analysis of both the
combinational logic network and the clock distribution network simultaneously. The …
[PDF][PDF] Latch Modeling for Statistical Timing Analysis
SXSAR Daifeng, WDZ Pan - Department of ECE, University of Texas, Austin … - academia.edu
Latch based circuits are widely adopted in high performance circuits. But there is a lack of
accurate latch models for doing timing analysis. In this paper, we propose a new latch delay
model in the context of SSTA based on a new perspective of latch timing. The proposed
latch model also takes into account the external timing variations such as data slew. The
new latch model is integrated into SSTA by considering the timing analysis of both the
combinational logic network and the clock distribution network simultaneously. The …
accurate latch models for doing timing analysis. In this paper, we propose a new latch delay
model in the context of SSTA based on a new perspective of latch timing. The proposed
latch model also takes into account the external timing variations such as data slew. The
new latch model is integrated into SSTA by considering the timing analysis of both the
combinational logic network and the clock distribution network simultaneously. The …
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