Logic locking acts as powerful countermeasure against piracy and reverse engineering attacks on the Integrated circuit (IC) supply chain. Stripped functionality logic locking (SFLL) represents the state-of-the-art in logic locking. SFLL delivers high resilience against certain attacks; however, it can protect only a small fraction of the design. Moreover, it fails to achieve a high corruption rate at the circuit outputs. In this paper, we explore strategies for deploying SFLL in a way that optimizes both corruption rate and resilience while protecting a large fraction of the design. The proposed joint optimization framework leverages the principles of VLSI testing to meet desired objectives cost-effectively.