Spiking Neural Network (SNN) is an artificial intelligence approach inspired by mammalian brain. Recent research has explored SNNs in Network-on-Chip (NoC) electronic circuits with the aim to deal with spatiotemporal dynamic tasks in real time. For the NoC-based hardware SNNs, their interconnections are suffering from large area overhead and power consumption due to the numerous buffers and complex structures of routers. This paper presents a novel Multi-Ring Interconnected Architecture (MRIA) to address this problem. Specifically, multiple unidirectional ring topologies are incorporated in MRIA to simplify the routers' crossbar switches, control logic and routing calculation units, and to decrease the interconnections' hardware area and power consumption. In addition, many buffers are also eliminated to further reduce interconnection costs. Experimental results demonstrate that compared to prior approaches, the proposed MRIA achieves average 20.3X and 7.9X reductions for the router area and power, respectively. Meantime, a high throughput of two million spikes per second is obtained.