[CITATION][C] On the likelihood of multiple bit upsets in logic circuits
PR Nanditha, S Shahbaz, PD Madhav - arXiv preprint arXiv:1401.1003, 2014
On the likelihood of multiple bit upsets in logic circuits
Soft errors have a significant impact on the circuit reliability at nanoscale technologies. At the
architectural level, soft errors are commonly modeled by a probabilistic bit-flip model. In
developing such abstract fault models, an important issue to consider is the likelihood of
multiple bit errors caused by particle strikes. This likelihood has been studied to a great
extent in memories, but has not been understood to the same extent in logic circuits. In this
paper, we attempt to quantify the likelihood that a single transient event can cause multiple …
architectural level, soft errors are commonly modeled by a probabilistic bit-flip model. In
developing such abstract fault models, an important issue to consider is the likelihood of
multiple bit errors caused by particle strikes. This likelihood has been studied to a great
extent in memories, but has not been understood to the same extent in logic circuits. In this
paper, we attempt to quantify the likelihood that a single transient event can cause multiple …
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