Optimization of area in digit-serial multiple constant multiplications at gate-level
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011•ieeexplore.ieee.org
The last two decades have seen many efficient algorithms and architectures for the design of
low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation, that
dominates the complexity of Digital Signal Processing (DSP) systems. On the other hand,
digit-serial architectures offer alternative low-complexity designs, since digit-serial operators
occupy less area and are independent of the data wordlength. This paper introduces the
problem of designing a digit-serial MCM operation with minimal area at gate-level and …
low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation, that
dominates the complexity of Digital Signal Processing (DSP) systems. On the other hand,
digit-serial architectures offer alternative low-complexity designs, since digit-serial operators
occupy less area and are independent of the data wordlength. This paper introduces the
problem of designing a digit-serial MCM operation with minimal area at gate-level and …
The last two decades have seen many efficient algorithms and architectures for the design of low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation, that dominates the complexity of Digital Signal Processing (DSP) systems. On the other hand, digit-serial architectures offer alternative low-complexity designs, since digit-serial operators occupy less area and are independent of the data wordlength. This paper introduces the problem of designing a digit-serial MCM operation with minimal area at gate-level and presents the exact formalization of the area optimization problem as a 0-1 Integer Linear Programming (ILP) problem. Experimental results show the efficiency of the proposed algorithm and digit- serial MCM designs in terms of area at gate-level.
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