Polychrony for formal refinement-checking in a system-level design methodology
The productivity gap incurred by the rising complexity of the system-on-chip design have
necessitated newer design paradigms to be introduced based on system-level design
languages. A gating factors for widespread adoption of these new paradigms is a lack of
formal tool support of fefinement based design. A system level representation may be
refined manually (in absence of adequate behavior synthesis algorithms and tools) to obtain
an implementation, but proving that the lower level representation preserves the correctness …
necessitated newer design paradigms to be introduced based on system-level design
languages. A gating factors for widespread adoption of these new paradigms is a lack of
formal tool support of fefinement based design. A system level representation may be
refined manually (in absence of adequate behavior synthesis algorithms and tools) to obtain
an implementation, but proving that the lower level representation preserves the correctness …
[CITATION][C] Polychrony for Formal Refinement Checking in a System-Level Design Methodology, Application of Concurrency to System Design (ACSD)
J Talpin, P Guernic, S Shukla, R Gupta, F Doucet - 2003 - IEEE
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