Power optimization techniques for SRAM-based FPGAS
S Mondal, SO Memik - 2006 International Conference on Field …, 2006 - ieeexplore.ieee.org
S Mondal, SO Memik
2006 International Conference on Field Programmable Logic and …, 2006•ieeexplore.ieee.orgIn this work, the authors aim to improve the power efficiency of FPGAs by proposing two
power reduction techniques: the authors present a low-penalty optimization technique to
reduce leakage power consumption in FPGA logic blocks by exploiting the variance in LUT
utilization across different designs (Mondal and Memik,(2005)), and presents a dual-V dd-
dual-V t routing architecture to reduce interconnect power consumption by using two levels
of V dd and V t (Mondal and Memik,(2005))
power reduction techniques: the authors present a low-penalty optimization technique to
reduce leakage power consumption in FPGA logic blocks by exploiting the variance in LUT
utilization across different designs (Mondal and Memik,(2005)), and presents a dual-V dd-
dual-V t routing architecture to reduce interconnect power consumption by using two levels
of V dd and V t (Mondal and Memik,(2005))
In this work, the authors aim to improve the power efficiency of FPGAs by proposing two power reduction techniques: the authors present a low-penalty optimization technique to reduce leakage power consumption in FPGA logic blocks by exploiting the variance in LUT utilization across different designs (Mondal and Memik, (2005)), and presents a dual-V dd -dual-V t routing architecture to reduce interconnect power consumption by using two levels of V dd and V t (Mondal and Memik, (2005))
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