We present a unified technique for timing verification and performance analysis of complex asynchronous circuits designed with implicit timing assumptions. We model interacting asynchronous controllers and datapath elements using timing constraint graphs. Performance metrics and circuit timing constraints to be checked are formulated as time separations between appropriate events. Time separations between all pairs of events are then efficiently computed in a single pass. We present results of analyzing a real asynchronous differential equation solver chip using our proposed technique, thereby demonstrating the practicality of our approach.