Device scaling and large-scale integration have led to growing concerns about soft errors in
microprocessors. To date, in all but the most demanding applications, implementing parity
and ECC for caches and other large, regular SRAM structures have been sufficient to stem
the growing soft error tide. This will not be the case for long and questions remain as to the
best way to detect and recover from soft errors in the remainder of the processor-in
particular, the less structured execution core. In this work, we propose the ReStore …

Device scaling and large scale integration have led to growing concerns about soft errors in
microprocessors. To date, in all but the most demanding applications, implementing parity
and ECC for caches and other large, regular SRAM structures have been sufficient to stem
the growing soft error tide. This will not be the case for long, and questions remain as to the
best way to detect and recover from soft errors in the remainder of the processor—in
particular, the less structured execution core. In this work, we propose the ReStore …