Ferroelectric (FE) FETs as nonvolatile memories have enjoyed a recent resurgence among emerging memory technologies due to the discovery of ferroelectricity in HfO 2 [1] . FE-HfO 2 offers attractive qualities such as CMOS compatibility, fast read/write speed, excellent retention, and scalability [2] . However, as write endurance remains a concern, various techniques have been proposed to improve endurance; among them, popular ones include engineering of the interfacial layer (IL), modulating the FE oxide properties, and changing the gate electrode [ 2 - 5 ]. In this work, we demonstrate for the first time a systematic, reliable, and rapid method to qualitatively predict the FE endurance of prospective gate stack designs prior to running a full FeFET fabrication process. MOSCAPs incorporating FE gate stacks (∼ 4.5 nm) realized via a one-step lithography process on highly doped Si are compared against real endurance results from SOI FeFETs incorporating the same FE oxides. The FeFETs demonstrated in this work boast impressive programmability (0.4 - 0.5V memory window at ±3.3V, 1 µ s) and a strong potential for further scalability.