As the minimum VLSI feature size continues to scale down to the 0.1–0.2-µm regime, the
need for low-resistance local interconnections will become increasingly critical. Although
reduction in the MOSFET channel length will remain the dominant factor in achieving higher
circuit performance, existing local interconnection materials will impose greater than
acceptable performance limitations. We review the state-of-the-art salicide and polycide
processes, with emphasis on work at IBM, and discuss the limitations that pertain to future …

As the minimum VLSI feature size continues to scale down to the 0.1-0.2-μm regime, the
need for low-resistance local interconnections will become increasingly critical. Although
reduction in the MOSFET channel length will remain the dominant factor in achieving higher
circuit performance, existing local interconnection materials will improse greater than
acceptable performance limitations. We review the state-of-the-art salicide and polycide
processes, with emphasis on work at IBM, and discuss the limitations that pertain to future …