FPGA placement and routing is time consuming, often serving as the major obstacle
inhibiting a fast edit-compile-test loop in prototyping and development and the major
obstacle preventing late-bound hardware and design mapping for reconfigurable systems.
We introduce a stochastic search scheme which can achieve comparable route quality to
traditional, software-based routers while being amenable to parallel, spatial implementation.
We quantify the quality and performance of this route scheme using the Toronto Place-and …