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11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology

…, N Ookuma, H Yabe, S Taigor… - … Solid-State Circuits …, 2017 - ieeexplore.ieee.org
High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND
flash from further reduction in die size, (eg, there is no ISSCC paper discussing a 3b/…

A 34 MB/s MLC write throughput 16 Gb NAND with all bit line architecture on 56 nm technology

…, A Li, F Pan, S Yadala, S Taigor… - IEEE Journal of Solid …, 2008 - ieeexplore.ieee.org
A 16 Gb 4-state MLC NAND flash memory augments the sustained program throughput to
34 MB/s by fully exercising all the available cells along a selected word line and by using …

A 34MB/s-program-throughput 16Gb MLC NAND with all-bitline architecture in 56nm

…, A Li, F Pan, S Yadala, S Taigor… - … Solid-State Circuits …, 2008 - ieeexplore.ieee.org
In the diverse world of NAND flash applications, higher storage capacity is not the only
imperative. Increasingly, performance is a differentiating factor and is also a way of creating new …

BOOSTER: Rethinking the erase operation of low-latency SSDs to achieve high throughput and less long latency

T Fujimori, S Nomura - Proceedings of the 16th ACM International …, 2023 - dl.acm.org
The disregarded performance of erase operation in low-latency NAND flash memory
relatively increases the impact of garbage collection interferences, which is a challenge when …

[CITATION][C] CMOS Class E Power Amplifier for Wireless Communications

SP Taigor - 2002 - Indian Institute of Technology …

[CITATION][C] 11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology. In 2017 IEEE International Solid-State Circuits Conference (ISSCC)

…, H Chibvongodze, N Ookuma, H Yabe, S Taigor… - 2017
Did you mean to search for: Subodh Tagore