Time-Mode z-1 Programmable Multiplier
O Panetas-Felouris, S Vlassis - 2022 29th IEEE International …, 2022 - ieeexplore.ieee.org
2022 29th IEEE International Conference on Electronics, Circuits …, 2022•ieeexplore.ieee.org
This paper proposes a novel circuit of az^-1 time-mode programmable multiplier with
improved accuracy which can be used as a basic building block in time-mode filtering and
signal processing. The proposed circuit is based on the time register topology which
employs the capacitor discharging approach. The circuit is built using 28 nm Samsung FD-
SOI process with a 1 V supply voltage. The sampling frequency is 5 MH_Z, and the average
current consumption is 102μA,. The circuit performance is verified through simulations …
improved accuracy which can be used as a basic building block in time-mode filtering and
signal processing. The proposed circuit is based on the time register topology which
employs the capacitor discharging approach. The circuit is built using 28 nm Samsung FD-
SOI process with a 1 V supply voltage. The sampling frequency is 5 MH_Z, and the average
current consumption is 102μA,. The circuit performance is verified through simulations …
This paper proposes a novel circuit of a time-mode programmable multiplier with improved accuracy which can be used as a basic building block in time-mode filtering and signal processing. The proposed circuit is based on the time register topology which employs the capacitor discharging approach. The circuit is built using 28 Samsung FD-SOI process with 1 supply voltage. The sampling frequency is 5 and the average current consumption is ,. The circuit performance is verified through simulations, featuring a linear programmable multiplication coefficient between 0.05 and 1 with a step of 0.01.
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