A 22nm 96KX144 RRAM macro with a self-tracking reference and a low ripple charge pump to achieve a configurable read window and a wide operating voltage …
…, WC Chen, WC Tsai, WT Chu, TC Ong… - … IEEE Symposium on …, 2020 - ieeexplore.ieee.org
An RRAM macro equips a hybrid self-tracking reference and a low ripple charge pump is
presented. It realizes configurable read windows and a consistent write performance at …
presented. It realizes configurable read windows and a consistent write performance at …
50-Å gate-Oxide MOSFET's at 77 K
TC Ong, PK Ko, C Hu - IEEE Transactions on Electron Devices, 1987 - ieeexplore.ieee.org
While hot-carrier-induced degradation is aggravated at cryogenic temperature, a very thin
gate-oxide (52-Å) device can still tolerate a 3-V power-supply voltage at 77 K. Hot-carrier-…
gate-oxide (52-Å) device can still tolerate a 3-V power-supply voltage at 77 K. Hot-carrier-…
Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology
…, KF Lin, CY Huang, YD Chih, TC Ong… - … Solid-State Circuits …, 2013 - ieeexplore.ieee.org
Spin-transfer-torque (STT) MRAM is considered as a good candidate for next-generation
memory that can replace Flash, SRAM and DRAM as well. As a replacement of SRAM or DRAM…
memory that can replace Flash, SRAM and DRAM as well. As a replacement of SRAM or DRAM…
The positive trigger voltage lowering effect for latch-up
…, WT Weng, JR Shih, KF Yu, TC Ong - Proceedings of the 11th …, 2004 - ieeexplore.ieee.org
In this paper, a new latch-up phenomenon, in which the positive trigger voltage V/sub trg+/
is smaller than the theoretical value, based on the two-step activation diode model, is found …
is smaller than the theoretical value, based on the two-step activation diode model, is found …
The embedded SCR NMOS and low capacitance ESD protection device
…, KR Peng, RY Chang, TL Yu, TC Ong - Proceedings of the …, 2002 - ieeexplore.ieee.org
Inserting the n-well and p+ diffusion into the drain region of NMOS transistor, the embedded
SCR NMOS (ESCR NMOS), without changing any DC IV characteristics of NMOS, and a …
SCR NMOS (ESCR NMOS), without changing any DC IV characteristics of NMOS, and a …
Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era
CH Diaz, MC Chang, TC Ong… - IEEE Journal of Solid …, 2003 - ieeexplore.ieee.org
… Tong-Chern Ong received the Bachelor degree in electrical engineering from the National
Taiwan University, Taipei, Taiwan, ROC, in 1976, and the Master and Ph.D degrees in …
Taiwan University, Taipei, Taiwan, ROC, in 1976, and the Master and Ph.D degrees in …
Low-side driver's failure mechanism in a class-D amplifier under short circuit test and a robust driver device
JH Lee, JR Shih, TC Ong, K Wu - 2010 IEEE International …, 2010 - ieeexplore.ieee.org
The failure mechanism in a class-D audio amplifier under short-circuit test is analyzed. The
damage, always in the low-side driver, is due to high current induced thermal run-away, …
damage, always in the low-side driver, is due to high current induced thermal run-away, …
A novel program disturb mechanism through erase gate in a 110nm sidewall split-gate Flash memory cell
…, J Huang, CJ Hwang, YT Lin, TC Ong… - Proceedings of 2011 …, 2011 - ieeexplore.ieee.org
In this paper, we present a new erase gate disturb mechanism during programming of
selected cell for split-gate Flash memory. This type of disturb occurs on the programmed cell …
selected cell for split-gate Flash memory. This type of disturb occurs on the programmed cell …
Logic process compatible 40nm 256K× 144 embedded RRAM with low voltage current limiter and ambient compensation scheme to improve the read window
…, CI Su, WC Chen, YC Lin, TC Ong… - 2018 IEEE Asian …, 2018 - ieeexplore.ieee.org
In this paper, we present a low voltage current limiter that can effectively confine the filament
size by limiting the write current to a preset compliance level after forming or SET operations…
size by limiting the write current to a preset compliance level after forming or SET operations…
A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O
…, JR Shih, YH Wu, KF Yu, TC Ong - 2005 IEEE International …, 2005 - ieeexplore.ieee.org
The gate voltage-induced current crowding (GVICC) effect (Lee, JH, et al., IRPS Proc., p.269-76,
2003) has been found to be the root cause of the failure of the high voltage tolerant I/O (…
2003) has been found to be the root cause of the failure of the high voltage tolerant I/O (…