For finite impulse response (FIR) filter implementation, fixed point arithmetic is frequently used, where truncation or rounding can be applied to round 2n-bit products of 2 n-bit numbers to n-bit products internally for decreasing power dissipation and space cost. Also, the multiplication can be done multiplierlessly by using single constant multiplication (SCM) or multiple constant multiplication (MCM) algorithms. This paper proposes truncated MCM using pattern modification technique (PMT) for FIR filter implementation. Comparisons of PMT and UT (uniformly truncation) are made with FPGA-based simulations. Results show that the proposed PMT algorithm can meet FIR filter specifications, and reduce area cost by 35%, compared to non-truncated MCM algorithms, without increasing quantization error.