Unified, ultra compact, quadratic power proxies for multi-core processors
M Yasin, A Shahrour, IAM Elfadel - 2014 Design, Automation & …, 2014 - ieeexplore.ieee.org
M Yasin, A Shahrour, IAM Elfadel
2014 Design, Automation & Test in Europe Conference & Exhibition …, 2014•ieeexplore.ieee.orgPer-core power proxies for multi-core processors are known to use several dozens of
hardware activity monitors to achieve a 2% accuracy on core power estimation. These
activity monitors are typically not accessible to the user, and even if they were accessible,
there would be a significant overhead in using them at the kernel or OS level for power
monitoring or control. Furthermore, when scaled up to hundreds of cores per chip, such
power proxies become a computational bottleneck for power management operations such …
hardware activity monitors to achieve a 2% accuracy on core power estimation. These
activity monitors are typically not accessible to the user, and even if they were accessible,
there would be a significant overhead in using them at the kernel or OS level for power
monitoring or control. Furthermore, when scaled up to hundreds of cores per chip, such
power proxies become a computational bottleneck for power management operations such …
Per-core power proxies for multi-core processors are known to use several dozens of hardware activity monitors to achieve a 2% accuracy on core power estimation. These activity monitors are typically not accessible to the user, and even if they were accessible, there would be a significant overhead in using them at the kernel or OS level for power monitoring or control. Furthermore, when scaled up to hundreds of cores per chip, such power proxies become a computational bottleneck for power management operations such as chip power capping. In this paper, we show that a 4% accuracy or better for per-core power estimation can be achieved using an ultra compact power proxy based on a hybrid set of only four user-accessible parameters, namely core frequency, core temperature, instruction-per-cycle and active-state residency. Our proxy is nonlinear, valid across all P and C states, and is based on a randomized power data collection strategy that aims at exercising all the P and C levels of each core. We illustrate the accuracy of the model using the full suite of the SPEC CPU 2006 benchmarks on a 12-core processor.
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