IEICE Trans - An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC

An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC

Chung-Ming CHEN
Chung-Ho CHEN

Publication
IEICE TRANSACTIONS on Information and Systems Vol.E90-D No.1 pp.99-107
Publication Date: 2007/01/01
Online ISSN: 1745-1361
DOI:
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Advanced Image Technology)
Category:
Keyword:
deblocking filter, H.264/AVC, video coding,

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Summary:
In this paper, we study and analyze the computational complexity of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a novel processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by four times when compared to the software implementation. Moreover, the system performance of our design significantly outperforms the previous proposals.

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